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Blues Cygnet Initialization#2950

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fpistm merged 6 commits intostm32duino:mainfrom
zfields:zak-cygnet-init
Apr 1, 2026
Merged

Blues Cygnet Initialization#2950
fpistm merged 6 commits intostm32duino:mainfrom
zfields:zak-cygnet-init

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@zfields zfields commented Mar 31, 2026

Fixes #2930

zfields added 6 commits March 19, 2026 14:18
Fixes clock initialization clash by mirroring Nucleo L432KC init.

Reported to Blues here: https://discuss.blues.com/t/wire-begin-causes-mcu-reset-hang-on-cygnet/3486

    Identifies odd dependency between Wire and USB.

stm32duino issue: stm32duino#2930

    Identifies clock config as possible root cause.
@fpistm fpistm added enhancement New feature or request fix 🩹 Bug fix labels Apr 1, 2026
@github-project-automation github-project-automation bot moved this from In progress to Reviewer approved in STM32 core based on ST HAL Apr 1, 2026
@fpistm fpistm added this to the 2.13.0 milestone Apr 1, 2026
@fpistm fpistm merged commit 7434813 into stm32duino:main Apr 1, 2026
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@github-project-automation github-project-automation bot moved this from Reviewer approved to Done in STM32 core based on ST HAL Apr 1, 2026
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enhancement New feature or request fix 🩹 Bug fix

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Wire.begin() and USB peripheral clock conflict

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