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Cortex-M backend: Add CortexMConfiguration#19505

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Erik-Lundell:cortex_m_configuration
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Cortex-M backend: Add CortexMConfiguration#19505
Erik-Lundell wants to merge 1 commit into
pytorch:mainfrom
Erik-Lundell:cortex_m_configuration

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The configuration mirrors cmsis_nn's CortexM enum, with an added ANY value, and a .backend convenience function.

Add the configuration to CortexM's pass manager as an optional parameter that defaults to ANY. If a pass wants it, pass it (analogous to the current exported_program handling).

Change-Id: I7c4fac9fca8c58672ca344ecfbc240ac17fdf063

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The configuration mirrors cmsis_nn's CortexM enum,
with an added ANY value, and a .backend convenience
function.

Add the configuration to CortexM's pass manager as an
optional parameter that defaults to ANY. If a pass
wants it, pass it (analogous to the current exported_program
handling).

Signed-off-by: Erik Lundell <erik.lundell@arm.com>
Change-Id: I7c4fac9fca8c58672ca344ecfbc240ac17fdf063
@Erik-Lundell Erik-Lundell requested a review from rascani as a code owner May 12, 2026 08:19
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pytorch-bot Bot commented May 12, 2026

🔗 Helpful Links

🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/19505

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@meta-cla meta-cla Bot added the CLA Signed This label is managed by the Facebook bot. Authors need to sign the CLA before a PR can be reviewed. label May 12, 2026
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rascani added a commit to rascani/executorch that referenced this pull request May 13, 2026
Aligns CortexMTargetConfig with the design Erik proposes in pytorch#19505
while keeping the wider plumbing in place. The earlier
CortexMCompileConfig is renamed to CortexMTargetConfig (and its file
moved to target_config.py) to disambiguate from EdgeCompileConfig —
this dataclass models a compilation *target*, not a step in the
compile pipeline.

Adopted from Erik's feedback:

* CortexM enum replaces the Cpu/Isa Literals — typo-safe and
  IDE-friendly.
* `.backend` property returns `cmsis_nn.Backend` directly, resolved
  via `cmsis_nn.resolve_backend(cmsis_nn.CortexM.<X>)`. The
  hand-rolled `_CPU_DEFAULT_ISA` dict is gone — cmsis_nn is the
  single source of truth for the CPU → backend mapping.
* CortexMPass abstract base class added; CortexMPassManager.transform()
  uses signature inspection to inject both `exported_program` and
  `target_config` into passes that declare them (mirroring Erik's
  proposal). The pass manager also gains stricter validation — the
  exported_program must be a real ExportedProgram and the pass list
  must contain classes, not instances — failing fast instead of
  producing opaque errors deep in _transform.
* cmsis_nn is now a hard dependency for the cortex_m tests: the
  top-level `import cmsis_nn` in test_target_config.py replaces the
  previous skipif-on-find_spec dance, addressing Erik's concern that
  skipping tests on missing deps can mask regressions.
* `+int8` dropped from cortex-m target strings — quantization is a
  result of the export flow, not a CPU attribute. TARGETS, help text,
  from_target_string, CI script and README aligned.
* Logging in `_to_edge_cortex_m` and the --delegate-ignored warning
  switched to f-strings.
* `__init__` docstring on CortexMPassManager documents the
  exported_program / passes / target_config defaults (including the
  M55+MVE fallback that matches pre-config behaviour).
* `import-not-found` removed from the cmsis_nn type-ignore — only
  `import-untyped` actually fires, and if cmsis_nn ever ships stubs
  the unused ignore will become a tripwire.

Kept the optional `isa` override field for the optional-extension
cases (M55 without MVE, M33 without DSP, etc.) — different from
Erik's enum-only design, but the override remains useful for cores
where ISA extensions are optional. A `_SUPPORTED_BACKENDS` table
encodes the per-CPU architectural capability set so overrides
validate at construction; forcing MVE on an M0 raises ValueError
with the actual supported list. The SCALAR ⊂ DSP ⊂ MVE supersession
reflects that an MVE-capable core also runs DSP and scalar code.

Defers Erik's `ANY` proposal. In pytorch#19505 ANY falls back to MVE, but an
honest "any cortex-m" choice would have to do worst-case scratch
buffer planning across the ISA classes (which may not be MVE).
Deferring until the scratch-buffer side lands and we can implement
the worst-case analysis properly.

Authored with Claude.
Comment thread backends/cortex_m/passes/cortex_m_pass_manager.py
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