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Add try_enable_x2apic() which reads IA32_APIC_BASE, sets bits 10+11 (x2APIC enable + global enable), writes back, and verifies via readback. Must be called before init_apic_mode() so the mode cache sees x2APIC. The dispatch layer (local_apic_read/write/eoi/id) already handled x2APIC via x2apic_read/x2apic_write MSR helpers — this activates that path. Verified in QEMU (-cpu max): x2APIC enabled, APIC mode: x2apic, LAPIC timer interrupt received successfully, full boot completes. Also update x2apic-prep.md: all four phases now complete.
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What
Adds
try_enable_x2apic()which enables x2APIC mode at boot if CPUID reports support.Called before
init_apic_mode()so the mode cache sees x2APIC, not xAPIC.How it works
CpuFeatures::get().x2apic— early-return with log if unsupportedIA32_APIC_BASE(MSR 0x1B) — early-return if already enabled (idempotent)init_apic_mode()then cachesApicAccessMode::X2ApicThe dispatch layer (
local_apic_read/write/eoi/id) already handled x2APIC via MSR paths — this activates that path.Verified in QEMU
Full boot completes including ACPI, PCI scan, USB/xHCI keyboard enumeration.
Docs
docs/plans/x2apic-prep.mdupdated — all four phases now marked complete.Changes
kernel/src/interrupts/apic.rs:try_enable_x2apic()+log_error!importkernel/src/interrupts/mod.rs: re-exporttry_enable_x2apickernel/src/environment.rs: calltry_enable_x2apic()beforeinit_apic_mode()docs/plans/x2apic-prep.md: all phases marked IMPLEMENTED