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Add 32 bits RISC-V support#89

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occheung wants to merge 2 commits intoedef1c:masterfrom
occheung:riscv
Open

Add 32 bits RISC-V support#89
occheung wants to merge 2 commits intoedef1c:masterfrom
occheung:riscv

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Summary

This patch is to add riscv32 target support to libfringe.

Changes

arch/riscv32.rs: Implemented a riscv32 port similar to other supported targets.
mod.rs: Point imp to riscv32.rs when using riscv32 target.

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