ports/stm32: Add Zephyr BLE support for WB55 and PYBD.#20
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Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
Add Zephyr BLE variant configuration for PYBD_SF6 board, with HCI UART readpacket support for bulk reading from the BT coprocessor. Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
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Summary
Adds Zephyr BLE integration for the STM32 port, targeting the NUCLEO_WB55 and PYBD_SF6 boards. The WB55's BLE controller runs on the M0+ coprocessor (CPU2) and communicates with the M4 host via IPCC mailbox — the HCI driver in
mpzephyrport.cbridges this to the Zephyr BLE host's H4 transport.The IPCC/rfcore integration required careful handling of the CPU2 lifecycle: HCI_Reset must not be sent to CPU2 as it corrupts all 192KB of SRAM1. This is prevented by a
drv_quirk_no_reset()hook in the Zephyr host'shci_core.c.Build variants:
NUCLEO_WB55 BOARD_VARIANT=zephyr_bleandPYBD_SF6 BOARD_VARIANT=zephyr_ble.Depends on #19.
Testing
11/11 BLE multitests passing on WB55 with nRF52840 DK as peripheral. PYBD variant builds but has not been tested with Zephyr BLE (PYBD is primarily used as a NimBLE reference central).
Trade-offs and Alternatives
The STM32 integration touches several files beyond the BLE-specific code (linker scripts, FreeRTOS hooks, system_stm32 changes) because the WB55's dual-core architecture and IPCC memory layout require careful memory section placement. These changes are guarded by
MICROPY_BLUETOOTH_ZEPHYRdefines where possible.Generative AI
I used generative AI tools when creating this PR, but a human has checked the code and is responsible for the description above.