Skip to content
View KaidenHsu's full-sized avatar

Highlights

  • Pro

Block or report KaidenHsu

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
KaidenHsu/README.md

Hi there, I'm Kaiden! πŸ‘‹

πŸš€ Prospective System Architect, Digital IC Designer

🏫 Education

</> Languages

Verilog

SystemVerilog

C

CPlusPlus

Python



πŸ”¨ Tools

Linix

Xilinx

RISC-V

Gem5



πŸ“ˆ GitHub Stats

🎯 2026 goal: familiarizing myself with ESL methodology and VLSI backend flow

Pinned Loading

  1. STN-Network STN-Network Public

    Forked from hankshyu/STN-Network

    Code to my ISASD, 2024 paper "An Improved Spatial Transformer Network based on Lightweight Localization Net (L-STN)"

    Jupyter Notebook 1

  2. Back-Angle-Measurement-Using-YOLOv8 Back-Angle-Measurement-Using-YOLOv8 Public

    Code to my IJETI, 2026 paper "Real-Time Video-Based Measurement of Back Angles Using YOLOv8 and Edge Detection for Strength Training"

    Python 1

  3. SOPC-System-Design SOPC-System-Design Public

    homework and labs for "SOPC Design Practice and FPGA System Design (2026 Spring)" in NSYSU, Taiwan

    Verilog

  4. DLab DLab Public

    An implementation-oriented digital FPGA design course in NYCU

    Verilog

  5. Open-Source-Prototype-Systems Open-Source-Prototype-Systems Public

    course projects for "Open Source Prototype Systems and Applications (2026 Spring)" in NSYSU, Taiwan

    SystemVerilog 1

  6. Computer-Architecture Computer-Architecture Public

    projects for "Computer Architecture (2026 Spring)" in NSYSU, Taiwan

    Assembly