π Prospective System Architect, Digital IC Designer
- M.S. Electrical Engineering (SoC subgroup) @ NSYSU, Taiwan (System Co-Design Lab)
- research focus: combine system co-design, FPGA acceleration, digital IC design with biomedical and scientific applications
- tools: Gem5, Verilator, RISC-V, Xilinx Alveo U55c FPGA Accelerator Card
- keywords: domain specific architecuture (DSA), electronic system level (ESL), digital IC design, FPGA prototyping, system co-design, hardware-software co-design, HBM
- B.S. Computer Science (AI subgroup) @ NCCU, Taiwan
- research focus: AI model architecture optimization, AI edge applications
- An Improved Spatial Transformer Network based on Lightweight Localization Net (L-STN) (ISASD 2024)
- Real-Time Video-Based Measurement of Back Angles Using YOLOv8 and Edge Detection for Strength Training (IJETI 2026)
π― 2026 goal: familiarizing myself with ESL methodology and VLSI backend flow



