Riscv settings file message confusing

[dcz-self]

While trying to update gd32vf103-pac, I got:

[WARN  svd2rust::generate::device] No settings file provided for RISC-V target. Using legacy interrupts rendering
[WARN  svd2rust::generate::device] Please, consider migrating your PAC to riscv 0.12.0 or later

The first count of confusion is that the message doesn't go away after bumping the riscv dependency.

The second count of confusion is the lack of explanation about what the setting file is. The README here is silent, and there doesn't seem to be a mention in the riscv crate docs. This error message could benefit from printing a link to some documentation.

[burrbull]

cc @romancardenas

[romancardenas]

@dcz-self new versions of riscv and riscv-rt rely on abstractions such as riscv-pac to adapt to particularities of the target chip.

Take a look at how we do this for the e310x chips.

You can check all the available riscv_config field here: https://github.com/rust-embedded/svd2rust/blob/master/src/config/riscv.rs

• core_interrupts: A list of interrupt sources that are handled by the core itself. If you do not specify this field, thensvd2rust assumes your target is compatible with the standard interrupt enumeration and re-exports it from riscv
• exceptions: list of exceptions in the chip. Again, if you do not specify this field, then the standard exception enum from riscv is used
• priorities: if your target has a standard interrupt peripheral (currently we only support PLIC), use this field to enumerate the priority levels in your system. It will implement riscv-pac traits for compatibility reasons.
• harts: enumerate the hart IDs of all the harts in your chip.
• clint and plic: if your chip has a PLIC or a CLINT peripheral, use this config field to use the standard peripherals from riscv-peripheral
• base_isa: specify the base ISA of your target. This will add a few lines of code in build.rs to declare environment variables required by riscv-rt's macros to generate valid code.
• mtvec_align: if your target supports vectored mode, it will probably present demanding alignment constraints for the interrupt vector table. For example, for E310x, the table must be 64-byte aligned. If you do not include this field, then alignment is set to 4, which is the minimum required by the RISC-V standard

I agree with you that documentation is insufficient and that warning messages might not be self-explanatory. I will try to address these issues ASAP

Check how the svd2rust command should be used here: https://github.com/riscv-rust/e310x/blob/50e2d6d0b0bac47edc962167980bc68583601e2d/e310x/update.sh#L8

[dcz-self]

Thanks for the info. It looks like quite an invasive change, so maybe I won't just jump to it so eagerly...

[kurtjd]

If it helps, here is an example of how I use a config.yml with the settings mentioned above for my PAC: https://github.com/kurtjd/embassy-neorv32/blob/main/neorv32-pac/config.yml

Seems to be working quite well for me so far!