diff --git a/.circleci/config.yml b/.circleci/config.yml index 30050b049..9fca2106a 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -330,29 +330,29 @@ workflows: - EOL_t480-hotp-maximized - build: - name: EOL_UNTESTED_optiplex-7010_9010-maximized - target: EOL_UNTESTED_optiplex-7010_9010-maximized + name: EOL_optiplex-7010_9010-maximized + target: EOL_optiplex-7010_9010-maximized subcommand: "" requires: - EOL_t480-hotp-maximized - build: - name: EOL_UNTESTED_optiplex-7010_9010-hotp-maximized - target: EOL_UNTESTED_optiplex-7010_9010-hotp-maximized + name: EOL_optiplex-7010_9010-hotp-maximized + target: EOL_optiplex-7010_9010-hotp-maximized subcommand: "" requires: - EOL_t480-hotp-maximized - build: - name: EOL_UNTESTED_optiplex-7010_9010_TXT-maximized - target: EOL_UNTESTED_optiplex-7010_9010_TXT-maximized + name: EOL_optiplex-7010_9010_TXT-maximized + target: EOL_optiplex-7010_9010_TXT-maximized subcommand: "" requires: - EOL_t480-hotp-maximized - build: - name: EOL_UNTESTED_optiplex-7010_9010_TXT-hotp-maximized - target: EOL_UNTESTED_optiplex-7010_9010_TXT-hotp-maximized + name: EOL_optiplex-7010_9010_TXT-hotp-maximized + target: EOL_optiplex-7010_9010_TXT-hotp-maximized subcommand: "" requires: - EOL_t480-hotp-maximized @@ -386,8 +386,8 @@ workflows: - EOL_t480-hotp-maximized - build: - name: EOL_UNTESTED_w530-hotp-maximized - target: EOL_UNTESTED_w530-hotp-maximized + name: EOL_w530-hotp-maximized + target: EOL_w530-hotp-maximized subcommand: "" requires: - EOL_t480-hotp-maximized @@ -400,8 +400,8 @@ workflows: - EOL_t480-hotp-maximized - build: - name: EOL_UNTESTED_w530-maximized - target: EOL_UNTESTED_w530-maximized + name: EOL_w530-maximized + target: EOL_w530-maximized subcommand: "" requires: - EOL_t480-hotp-maximized @@ -421,15 +421,15 @@ workflows: - EOL_t480-hotp-maximized - build: - name: EOL_UNTESTED_t440p-maximized - target: EOL_UNTESTED_t440p-maximized + name: EOL_t440p-maximized + target: EOL_t440p-maximized subcommand: "" requires: - EOL_t480-hotp-maximized - build: - name: EOL_UNTESTED_t440p-hotp-maximized - target: EOL_UNTESTED_t440p-hotp-maximized + name: EOL_t440p-hotp-maximized + target: EOL_t440p-hotp-maximized subcommand: "" requires: - EOL_t480-hotp-maximized diff --git a/BOARDS_AND_TESTERS.md b/BOARDS_AND_TESTERS.md index e1e84f64a..cbc9fda4f 100644 --- a/BOARDS_AND_TESTERS.md +++ b/BOARDS_AND_TESTERS.md @@ -49,13 +49,12 @@ xx30 (Ivy Bridge: Intel 3rd Gen CPU) - [ ] w530 (xx30): @eganonoa @zifxify @weyounsix (dGPU: w530-k2000m) @jnscmns (dGPU K1000M) @computer-user123 (w530 / w530 k2000: prefers iGPU) @tlaurio - [ ] x230 (xx30): @nestire @tlaurion @merge @jan23 @MrChromebox @shamen123 @eganonoa @bwachter @Thrilleratplay @jnscmns - [ ] x230-fhd/edp variant: @n4ru @computer-user123 (nitro caster board) @Tonux599 @househead @pcm720 (eDP 4.0 board and 1440p display) @doob85 https://matrix.to/#/@rsabdpy:matrix.org (agan mod board) -- [ ] x230t: @fhvyhjriur - [ ] t530 (xx30): @fhvyhjriur @3hhh (See: https://github.com/linuxboot/heads/issues/1682) xx4x (Haswell: Intel 4th Gen CPU) === -- [ ] t440p: @fhvyhjriur @ThePlexus @srgrint @akunterkontrolle @rbreslow -- [ ] w541 (similar of t440p): @ResendeGHF @gaspar-ilom (Late tested; at risk of deprecation) +- [ ] t440p: @MattClifton76 @fhvyhjriur @ThePlexus @srgrint @akunterkontrolle @rbreslow +- [ ] w541 (similar of t440p): @gaspar-ilom @ResendeGHF xx8x (Kaby Lake Refresh: Intel 8th Gen Mobile : ESU ended 12/31/2024) === diff --git a/Makefile b/Makefile index 9d033ce1e..5d0a0e65b 100644 --- a/Makefile +++ b/Makefile @@ -73,7 +73,9 @@ DATE=`date --rfc-3339=seconds` BOARD ?= qemu-coreboot-fbwhiptail-tpm1 -ifeq "y" "$(shell [[ $(BOARD) =~ (^EOL_|^)UNMAINTAINED_.* ]] && echo y)"" +# If the board name begins with UNMAINTAINED_, use the +# unmaintained_boards path. +ifeq "y" "$(shell echo '$(BOARD)' | grep -E '^UNMAINTAINED_' >/dev/null 2>&1 && echo y)" CONFIG := $(pwd)/unmaintained_boards/$(BOARD)/$(BOARD).config else CONFIG := $(pwd)/boards/$(BOARD)/$(BOARD).config diff --git a/blobs/haswell/.gitignore b/blobs/haswell/.gitignore deleted file mode 100644 index b3810c18c..000000000 --- a/blobs/haswell/.gitignore +++ /dev/null @@ -1 +0,0 @@ -mrc.bin diff --git a/blobs/haswell/obtain-mrc b/blobs/haswell/obtain-mrc deleted file mode 100755 index 3e87cab32..000000000 --- a/blobs/haswell/obtain-mrc +++ /dev/null @@ -1,45 +0,0 @@ -#!/usr/bin/env bash - -set -e - -function usage() { - echo -n \ - "Usage: $(basename "$0") path_to_output_directory -Obtain mrc.bin from a Haswell Chromebook firmware image. -" -} - -MRC_BIN_HASH="d368ba45096a3b5490ed27014e1f9004bc363434ffdce0c368c08a89c4746722" - -if [[ "${BASH_SOURCE[0]}" == "$0" ]]; then - if [[ "${1:-}" == "--help" ]]; then - usage - else - if [[ -z "${COREBOOT_DIR}" ]]; then - echo "ERROR: No COREBOOT_DIR variable defined." - exit 1 - fi - - output_dir="$(realpath "${1:-./}")" - - # Obtain mrc.bin from a Haswell Chromebook firmware image. - # https://doc.coreboot.org/northbridge/intel/haswell/mrc.bin.html#obtaining-mrc-bin - if [[ ! -f "${output_dir}/mrc.bin" ]]; then - pushd "${COREBOOT_DIR}" - - make -C util/cbfstool - cd util/chromeos - ./crosfirmware.sh peppy - ../cbfstool/cbfstool coreboot-*.bin extract -f mrc.bin -n mrc.bin -r RO_SECTION - - mv mrc.bin "${output_dir}/mrc.bin" - - popd - fi - - if ! echo "${MRC_BIN_HASH} ${output_dir}/mrc.bin" | sha256sum --check; then - echo "ERROR: SHA256 checksum for mrc.bin doesn't match." - exit 1 - fi - fi -fi diff --git a/blobs/t440p/README.md b/blobs/t440p/README.md index 79ddada13..9569b4128 100644 --- a/blobs/t440p/README.md +++ b/blobs/t440p/README.md @@ -7,14 +7,17 @@ Coreboot on the T440p requires the following binary blobs: -- `mrc.bin` - Consists of Intel’s Memory Reference Code (MRC) and [is used to initialize the DRAM](https://doc.coreboot.org/northbridge/intel/haswell/mrc.bin.html). - `me.bin` - Consists of Intel’s Management Engine (ME), which we modify using [me_cleaner](https://github.com/corna/me_cleaner) to remove all but the modules which are necessary for the CPU to function. - `gbe.bin` - Consists of hardware/software configuration data for the Gigabit Ethernet (GbE) controller. Intel publishes the data structure [here](https://web.archive.org/web/20230122164346/https://www.intel.com/content/dam/www/public/us/en/documents/design-guides/i-o-controller-hub-8-9-nvm-map-guide.pdf), and an [ImHex](https://github.com/WerWolv/ImHex) hex editor pattern is available [here](https://github.com/rbreslow/ImHex-Patterns/blob/rb/intel-ich8/patterns/intel/ich8_lan_nvm.hexpat). - `ifd.bin` - Consists of the Intel Flash Descriptor (IFD). Intel publishes the data structure [here](https://web.archive.org/web/20221208011432/https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/io-controller-hub-8-datasheet.pdf), and an ImHex hex editor pattern is available [here](https://github.com/rbreslow/ImHex-Patterns/blob/rb/intel-ich8/patterns/intel/ich8_flash_descriptor.hexpat). Heads supplies an IFD and GbE blob, which we extracted from a donor board. We changed the MAC address of the GbE blob to `00:de:ad:c0:ff:ee` using [nvmutil](https://libreboot.org/docs/install/nvmutil.html), to support anonymity and build reproducibility. -When building any T440p board variant with `make`, the build system will download a copy of the MRC and Intel ME. We extract `mrc.bin` from a Chromebook firmware image and `me.bin` from a Lenovo firmware update. +When building any T440p board variant with `make`, the build system will download a copy of the Intel ME. We extract the `me.bin` from a Lenovo firmware update. + +### Native Ram Initialization + +Note that due to native ram initialization for haswell boards in coreboot it is no longer necessary to use a third party blob (`mrc.bin`) for that. ## Using Your Own Blobs diff --git a/blobs/w541/README.md b/blobs/w541/README.md index 8e6bf5385..fae8190f5 100644 --- a/blobs/w541/README.md +++ b/blobs/w541/README.md @@ -7,15 +7,17 @@ Coreboot on the W541 requires the following binary blobs: -- `mrc.bin` - Consists of Intel’s Memory Reference Code (MRC) and [is used to initialize the DRAM](https://doc.coreboot.org/northbridge/intel/haswell/mrc.bin.html). - - Known issues with ram initilization are listed below. - `me.bin` - Consists of Intel’s Management Engine (ME), which we modify using [me_cleaner](https://github.com/corna/me_cleaner) to remove all but the modules which are necessary for the CPU to function. - `gbe.bin` - Consists of hardware/software configuration data for the Gigabit Ethernet (GbE) controller. Intel publishes the data structure [here](https://web.archive.org/web/20230122164346/https://www.intel.com/content/dam/www/public/us/en/documents/design-guides/i-o-controller-hub-8-9-nvm-map-guide.pdf), and an [ImHex](https://github.com/WerWolv/ImHex) hex editor pattern is available [here](https://github.com/rbreslow/ImHex-Patterns/blob/rb/intel-ich8/patterns/intel/ich8_lan_nvm.hexpat). - `ifd.bin` - Consists of the Intel Flash Descriptor (IFD). Intel publishes the data structure [here](https://web.archive.org/web/20221208011432/https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/io-controller-hub-8-datasheet.pdf), and an ImHex hex editor pattern is available [here](https://github.com/rbreslow/ImHex-Patterns/blob/rb/intel-ich8/patterns/intel/ich8_flash_descriptor.hexpat). Heads supplies an IFD and GbE blob, which we extracted from a donor board. We changed the MAC address of the GbE blob to `00:de:ad:c0:ff:ee` using [nvmutil](https://libreboot.org/docs/install/nvmutil.html), to support anonymity and build reproducibility. -When building any W541 board variant with `make`, the build system will download a copy of the MRC and Intel ME. We extract `mrc.bin` from a Chromebook firmware image and `me.bin` from a Lenovo firmware update. +When building any W541 board variant with `make`, the build system will download a copy of the Intel ME. We extract the `me.bin` from a Lenovo firmware update. + +### Native Ram Initialization + +Note that due to native ram initialization for haswell boards in coreboot it is no longer necessary to use a third party blob (`mrc.bin`) ## Using Your Own Blobs @@ -38,8 +40,4 @@ Now, you can rebuild Heads: ```console $ make BOARD=w541-hotp-maximized -``` - -# Known Issues -- Ram initialization with the MRC blob is very slow (~40s until boot splash) and so far native ram init (NRI) which was merged upstream has not been able to resolve the issue under heads. Work on HRI is tracked here: https://github.com/linuxboot/heads/pull/1923 -- S3 resume from suspend has been reported as flaky on some boards (4 DIMMs with a total of 32GB ram). +``` \ No newline at end of file diff --git a/boards/EOL_UNTESTED_optiplex-7010_9010-hotp-maximized/EOL_UNTESTED_optiplex-7010_9010-hotp-maximized.config b/boards/EOL_optiplex-7010_9010-hotp-maximized/EOL_optiplex-7010_9010-hotp-maximized.config similarity index 100% rename from boards/EOL_UNTESTED_optiplex-7010_9010-hotp-maximized/EOL_UNTESTED_optiplex-7010_9010-hotp-maximized.config rename to boards/EOL_optiplex-7010_9010-hotp-maximized/EOL_optiplex-7010_9010-hotp-maximized.config diff --git a/boards/EOL_UNTESTED_optiplex-7010_9010-maximized/EOL_UNTESTED_optiplex-7010_9010-maximized.config b/boards/EOL_optiplex-7010_9010-maximized/EOL_optiplex-7010_9010-maximized.config similarity index 100% rename from boards/EOL_UNTESTED_optiplex-7010_9010-maximized/EOL_UNTESTED_optiplex-7010_9010-maximized.config rename to boards/EOL_optiplex-7010_9010-maximized/EOL_optiplex-7010_9010-maximized.config diff --git a/boards/EOL_UNTESTED_optiplex-7010_9010_TXT-hotp-maximized/EOL_UNTESTED_optiplex-7010_9010_TXT-hotp-maximized.config b/boards/EOL_optiplex-7010_9010_TXT-hotp-maximized/EOL_optiplex-7010_9010_TXT-hotp-maximized.config similarity index 100% rename from boards/EOL_UNTESTED_optiplex-7010_9010_TXT-hotp-maximized/EOL_UNTESTED_optiplex-7010_9010_TXT-hotp-maximized.config rename to boards/EOL_optiplex-7010_9010_TXT-hotp-maximized/EOL_optiplex-7010_9010_TXT-hotp-maximized.config diff --git a/boards/EOL_UNTESTED_optiplex-7010_9010_TXT-maximized/EOL_UNTESTED_optiplex-7010_9010_TXT-maximized.config b/boards/EOL_optiplex-7010_9010_TXT-maximized/EOL_optiplex-7010_9010_TXT-maximized.config similarity index 100% rename from boards/EOL_UNTESTED_optiplex-7010_9010_TXT-maximized/EOL_UNTESTED_optiplex-7010_9010_TXT-maximized.config rename to boards/EOL_optiplex-7010_9010_TXT-maximized/EOL_optiplex-7010_9010_TXT-maximized.config diff --git a/boards/EOL_UNTESTED_t440p-hotp-maximized/EOL_UNTESTED_t440p-hotp-maximized.config b/boards/EOL_t440p-hotp-maximized/EOL_t440p-hotp-maximized.config similarity index 89% rename from boards/EOL_UNTESTED_t440p-hotp-maximized/EOL_UNTESTED_t440p-hotp-maximized.config rename to boards/EOL_t440p-hotp-maximized/EOL_t440p-hotp-maximized.config index 7350904c2..d176e98ad 100644 --- a/boards/EOL_UNTESTED_t440p-hotp-maximized/EOL_UNTESTED_t440p-hotp-maximized.config +++ b/boards/EOL_t440p-hotp-maximized/EOL_t440p-hotp-maximized.config @@ -51,12 +51,7 @@ CONFIG_HOTPKEY=y export CONFIG_AUTO_BOOT_TIMEOUT=5 # Make the Coreboot build depend on the following 3rd party blobs: -$(build)/coreboot-$(CONFIG_COREBOOT_VERSION)/$(BOARD)/.build: \ - $(pwd)/blobs/haswell/mrc.bin $(pwd)/blobs/t440p/me.bin - -$(pwd)/blobs/haswell/mrc.bin: - COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \ - $(pwd)/blobs/haswell/obtain-mrc $(pwd)/blobs/haswell +$(build)/coreboot-$(CONFIG_COREBOOT_VERSION)/$(BOARD)/.build: $(pwd)/blobs/t440p/me.bin $(pwd)/blobs/t440p/me.bin: COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \ diff --git a/boards/EOL_UNTESTED_t440p-maximized/EOL_UNTESTED_t440p-maximized.config b/boards/EOL_t440p-maximized/EOL_t440p-maximized.config similarity index 88% rename from boards/EOL_UNTESTED_t440p-maximized/EOL_UNTESTED_t440p-maximized.config rename to boards/EOL_t440p-maximized/EOL_t440p-maximized.config index 0566a1332..44c7f0cea 100644 --- a/boards/EOL_UNTESTED_t440p-maximized/EOL_UNTESTED_t440p-maximized.config +++ b/boards/EOL_t440p-maximized/EOL_t440p-maximized.config @@ -49,12 +49,7 @@ export CONFIG_BOARD_NAME="ThinkPad T440p-maximized" export CONFIG_FLASH_OPTIONS="flashprog --progress --programmer internal" # Make the Coreboot build depend on the following 3rd party blobs: -$(build)/coreboot-$(CONFIG_COREBOOT_VERSION)/$(BOARD)/.build: \ - $(pwd)/blobs/haswell/mrc.bin $(pwd)/blobs/t440p/me.bin - -$(pwd)/blobs/haswell/mrc.bin: - COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \ - $(pwd)/blobs/haswell/obtain-mrc $(pwd)/blobs/haswell +$(build)/coreboot-$(CONFIG_COREBOOT_VERSION)/$(BOARD)/.build: $(pwd)/blobs/t440p/me.bin $(pwd)/blobs/t440p/me.bin: COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \ diff --git a/boards/EOL_UNTESTED_w530-hotp-maximized/EOL_UNTESTED_w530-hotp-maximized.config b/boards/EOL_w530-hotp-maximized/EOL_w530-hotp-maximized.config similarity index 100% rename from boards/EOL_UNTESTED_w530-hotp-maximized/EOL_UNTESTED_w530-hotp-maximized.config rename to boards/EOL_w530-hotp-maximized/EOL_w530-hotp-maximized.config diff --git a/boards/EOL_UNTESTED_w530-maximized/EOL_UNTESTED_w530-maximized.config b/boards/EOL_w530-maximized/EOL_w530-maximized.config similarity index 100% rename from boards/EOL_UNTESTED_w530-maximized/EOL_UNTESTED_w530-maximized.config rename to boards/EOL_w530-maximized/EOL_w530-maximized.config diff --git a/boards/EOL_w541-hotp-maximized/EOL_w541-hotp-maximized.config b/boards/EOL_w541-hotp-maximized/EOL_w541-hotp-maximized.config index 1be4b547d..1f85ddf95 100644 --- a/boards/EOL_w541-hotp-maximized/EOL_w541-hotp-maximized.config +++ b/boards/EOL_w541-hotp-maximized/EOL_w541-hotp-maximized.config @@ -52,12 +52,7 @@ CONFIG_HOTPKEY=y export CONFIG_AUTO_BOOT_TIMEOUT=5 # Make the Coreboot build depend on the following 3rd party blobs: -$(build)/coreboot-$(CONFIG_COREBOOT_VERSION)/$(BOARD)/.build: \ - $(pwd)/blobs/haswell/mrc.bin $(pwd)/blobs/w541/me.bin - -$(pwd)/blobs/haswell/mrc.bin: - COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \ - $(pwd)/blobs/haswell/obtain-mrc $(pwd)/blobs/haswell +$(build)/coreboot-$(CONFIG_COREBOOT_VERSION)/$(BOARD)/.build: $(pwd)/blobs/w541/me.bin $(pwd)/blobs/w541/me.bin: COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \ diff --git a/boards/EOL_w541-maximized/EOL_w541-maximized.config b/boards/EOL_w541-maximized/EOL_w541-maximized.config index 7e02aa0ed..3fb2cb5bd 100644 --- a/boards/EOL_w541-maximized/EOL_w541-maximized.config +++ b/boards/EOL_w541-maximized/EOL_w541-maximized.config @@ -50,12 +50,7 @@ export CONFIG_BOARD_NAME="ThinkPad W541-maximized" export CONFIG_FLASH_OPTIONS="flashprog --progress --programmer internal" # Make the Coreboot build depend on the following 3rd party blobs: -$(build)/coreboot-$(CONFIG_COREBOOT_VERSION)/$(BOARD)/.build: \ - $(pwd)/blobs/haswell/mrc.bin $(pwd)/blobs/w541/me.bin - -$(pwd)/blobs/haswell/mrc.bin: - COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \ - $(pwd)/blobs/haswell/obtain-mrc $(pwd)/blobs/haswell +$(build)/coreboot-$(CONFIG_COREBOOT_VERSION)/$(BOARD)/.build: $(pwd)/blobs/w541/me.bin $(pwd)/blobs/w541/me.bin: COREBOOT_DIR="$(build)/$(coreboot_base_dir)" \ diff --git a/config/coreboot-optiplex-7019_9010-maximized.config b/config/coreboot-optiplex-7019_9010-maximized.config index 753a4f036..2b5158a75 100644 --- a/config/coreboot-optiplex-7019_9010-maximized.config +++ b/config/coreboot-optiplex-7019_9010-maximized.config @@ -127,7 +127,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Dell Inc." -CONFIG_CBFS_SIZE=0xBE4FFF +CONFIG_CBFS_SIZE=0xBDF000 # CONFIG_CONSOLE_SERIAL is not set CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 diff --git a/config/coreboot-optiplex-7019_9010_TXT-maximized.config b/config/coreboot-optiplex-7019_9010_TXT-maximized.config index bc35d35a3..31cf05d2e 100644 --- a/config/coreboot-optiplex-7019_9010_TXT-maximized.config +++ b/config/coreboot-optiplex-7019_9010_TXT-maximized.config @@ -127,7 +127,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" # CONFIG_NO_POST is not set CONFIG_MAINBOARD_VENDOR="Dell Inc." -CONFIG_CBFS_SIZE=0xBE4FFF +CONFIG_CBFS_SIZE=0xBDF000 # CONFIG_CONSOLE_SERIAL is not set CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 diff --git a/config/coreboot-t430-maximized.config b/config/coreboot-t430-maximized.config index 155cee16a..167b031a7 100644 --- a/config/coreboot-t430-maximized.config +++ b/config/coreboot-t430-maximized.config @@ -130,7 +130,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" CONFIG_NO_POST=y CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE4FFF +CONFIG_CBFS_SIZE=0xBDF000 CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 CONFIG_MAX_CPUS=8 diff --git a/config/coreboot-t440p.config b/config/coreboot-t440p.config index ee4f52ce3..1f7058919 100644 --- a/config/coreboot-t440p.config +++ b/config/coreboot-t440p.config @@ -129,7 +129,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" CONFIG_NO_POST=y CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE4FFF +CONFIG_CBFS_SIZE=0xBDF000 CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 CONFIG_MAX_CPUS=8 @@ -157,9 +157,9 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 CONFIG_TPM_PIRQ=0x0 CONFIG_DCACHE_RAM_BASE=0xff7c0000 -CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_DCACHE_RAM_SIZE=0x40000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 -CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_HAVE_INTEL_FIRMWARE=y CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 @@ -290,9 +290,7 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_HAVE_MRC=y -CONFIG_MRC_FILE="@BLOB_DIR@/haswell/mrc.bin" -CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 @@ -346,9 +344,7 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y # Northbridge # CONFIG_NORTHBRIDGE_INTEL_HASWELL=y -# CONFIG_USE_NATIVE_RAMINIT is not set -# CONFIG_USE_BROADWELL_MRC is not set -CONFIG_HASWELL_HIDE_PEG_FROM_MRC=y +CONFIG_USE_NATIVE_RAMINIT=y # # Southbridge @@ -710,6 +706,8 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y # General Debug Settings # # CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_MALLOC is not set diff --git a/config/coreboot-t530-dgpu-maximized.config b/config/coreboot-t530-dgpu-maximized.config index 85813cb21..adca3191f 100644 --- a/config/coreboot-t530-dgpu-maximized.config +++ b/config/coreboot-t530-dgpu-maximized.config @@ -119,7 +119,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" CONFIG_NO_POST=y CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE4FFF +CONFIG_CBFS_SIZE=0xBDF000 CONFIG_MAX_CPUS=8 CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_VGA_BIOS_DGPU_ID="10de,0def" diff --git a/config/coreboot-t530-maximized.config b/config/coreboot-t530-maximized.config index 92ad7bc65..fe1b11019 100644 --- a/config/coreboot-t530-maximized.config +++ b/config/coreboot-t530-maximized.config @@ -128,7 +128,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" CONFIG_NO_POST=y CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE4FFF +CONFIG_CBFS_SIZE=0xBDF000 CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 CONFIG_MAX_CPUS=8 diff --git a/config/coreboot-w530-dgpu-K1000m-maximized.config b/config/coreboot-w530-dgpu-K1000m-maximized.config index 3d0203766..3d1887dc7 100644 --- a/config/coreboot-w530-dgpu-K1000m-maximized.config +++ b/config/coreboot-w530-dgpu-K1000m-maximized.config @@ -119,7 +119,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" CONFIG_NO_POST=y CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE4FFF +CONFIG_CBFS_SIZE=0xBDF000 CONFIG_MAX_CPUS=8 CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_VGA_BIOS_DGPU_ID="10de,0ffc" diff --git a/config/coreboot-w530-dgpu-K2000m-maximized.config b/config/coreboot-w530-dgpu-K2000m-maximized.config index 8adc787fc..848741d33 100644 --- a/config/coreboot-w530-dgpu-K2000m-maximized.config +++ b/config/coreboot-w530-dgpu-K2000m-maximized.config @@ -119,7 +119,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" CONFIG_NO_POST=y CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE4FFF +CONFIG_CBFS_SIZE=0xBDF000 CONFIG_MAX_CPUS=8 CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_VGA_BIOS_DGPU_ID="10de,0ffb" diff --git a/config/coreboot-w530-maximized.config b/config/coreboot-w530-maximized.config index 48beed7a5..d09433218 100644 --- a/config/coreboot-w530-maximized.config +++ b/config/coreboot-w530-maximized.config @@ -129,7 +129,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" CONFIG_NO_POST=y CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE4FFF +CONFIG_CBFS_SIZE=0xBDF000 CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 CONFIG_MAX_CPUS=8 diff --git a/config/coreboot-w541.config b/config/coreboot-w541.config index 33d52e1f8..7615f3bfb 100644 --- a/config/coreboot-w541.config +++ b/config/coreboot-w541.config @@ -129,7 +129,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" CONFIG_NO_POST=y CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE4FFF +CONFIG_CBFS_SIZE=0xBDF000 CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 CONFIG_MAX_CPUS=8 @@ -157,9 +157,9 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout" CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 CONFIG_TPM_PIRQ=0x0 CONFIG_DCACHE_RAM_BASE=0xff7c0000 -CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_DCACHE_RAM_SIZE=0x40000 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000 -CONFIG_DCACHE_BSP_STACK_SIZE=0x2000 +CONFIG_DCACHE_BSP_STACK_SIZE=0x20000 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144 CONFIG_HAVE_INTEL_FIRMWARE=y CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 @@ -290,9 +290,7 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256 CONFIG_INTEL_GMA_BCLM_WIDTH=16 CONFIG_BOOTBLOCK_IN_CBFS=y -CONFIG_HAVE_MRC=y -CONFIG_MRC_FILE="@BLOB_DIR@/haswell/mrc.bin" -CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000 +CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0 CONFIG_HPET_MIN_TICKS=0x80 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000 @@ -346,9 +344,7 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y # Northbridge # CONFIG_NORTHBRIDGE_INTEL_HASWELL=y -# CONFIG_USE_NATIVE_RAMINIT is not set -# CONFIG_USE_BROADWELL_MRC is not set -CONFIG_HASWELL_HIDE_PEG_FROM_MRC=y +CONFIG_USE_NATIVE_RAMINIT=y # # Southbridge @@ -709,6 +705,8 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y # General Debug Settings # # CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_MALLOC is not set diff --git a/config/coreboot-x230-maximized-fhd_edp.config b/config/coreboot-x230-maximized-fhd_edp.config index 2191c2cef..d004f4a97 100644 --- a/config/coreboot-x230-maximized-fhd_edp.config +++ b/config/coreboot-x230-maximized-fhd_edp.config @@ -129,7 +129,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" CONFIG_NO_POST=y CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE4FFF +CONFIG_CBFS_SIZE=0xBDF000 CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 CONFIG_MAX_CPUS=8 diff --git a/config/coreboot-x230-maximized.config b/config/coreboot-x230-maximized.config index 4a6e95213..76b74fbdd 100644 --- a/config/coreboot-x230-maximized.config +++ b/config/coreboot-x230-maximized.config @@ -129,7 +129,7 @@ CONFIG_DIMM_SPD_SIZE=256 CONFIG_FMDFILE="" CONFIG_NO_POST=y CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_CBFS_SIZE=0xBE4FFF +CONFIG_CBFS_SIZE=0xBDF000 CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600 CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560 CONFIG_MAX_CPUS=8 diff --git a/patches/coreboot-25.09/0006-nb-intel-haswell-Use-boolean-for-cbmem_was_initted.patch b/patches/coreboot-25.09/0006-nb-intel-haswell-Use-boolean-for-cbmem_was_initted.patch new file mode 100644 index 000000000..5275b7e60 --- /dev/null +++ b/patches/coreboot-25.09/0006-nb-intel-haswell-Use-boolean-for-cbmem_was_initted.patch @@ -0,0 +1,44 @@ +From d9b609b139c619ea1fe8f2b442469992a6487fe5 Mon Sep 17 00:00:00 2001 +From: Elyes Haouas +Date: Thu, 2 Oct 2025 15:01:22 +0200 +Subject: [PATCH 06/11] nb/intel/haswell: Use boolean for cbmem_was_initted + +Change-Id: I4a311ce924200d85a97806bb3c826a374e68d81c +Signed-off-by: Elyes Haouas +Reviewed-on: https://review.coreboot.org/c/coreboot/+/89399 +Reviewed-by: Angel Pons +Tested-by: build bot (Jenkins) +--- + src/northbridge/intel/haswell/broadwell_mrc/raminit.c | 2 +- + src/northbridge/intel/haswell/haswell_mrc/raminit.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +index 5b2427b918..e96f1a3adf 100644 +--- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c ++++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +@@ -422,7 +422,7 @@ void perform_raminit(const int s3resume) + + intel_early_me_status(); + +- int cbmem_was_initted = !cbmem_recovery(s3resume); ++ bool cbmem_was_initted = !cbmem_recovery(s3resume); + if (s3resume && !cbmem_was_initted) { + /* Failed S3 resume, reset to come up cleanly */ + printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n"); +diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c +index 3d5e46cdac..62aa89ca79 100644 +--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c ++++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c +@@ -417,7 +417,7 @@ void perform_raminit(const int s3resume) + + intel_early_me_status(); + +- int cbmem_was_initted = !cbmem_recovery(s3resume); ++ bool cbmem_was_initted = !cbmem_recovery(s3resume); + if (s3resume && !cbmem_was_initted) { + /* Failed S3 resume, reset to come up cleanly */ + printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n"); +-- +2.47.3 + diff --git a/patches/coreboot-25.09/0007-nb-intel-haswell-acpi-Add-missing-MMIO-window-below-.patch b/patches/coreboot-25.09/0007-nb-intel-haswell-acpi-Add-missing-MMIO-window-below-.patch new file mode 100644 index 000000000..1ab9c58a4 --- /dev/null +++ b/patches/coreboot-25.09/0007-nb-intel-haswell-acpi-Add-missing-MMIO-window-below-.patch @@ -0,0 +1,132 @@ +From 74d7a213823eca265733630e2656ce502a3b5bfd Mon Sep 17 00:00:00 2001 +From: Matt DeVillier +Date: Wed, 15 Oct 2025 09:12:05 -0500 +Subject: [PATCH 07/11] nb/intel/haswell/acpi: Add missing MMIO window below + 4GB + +For Broadwell SoC boards (which use Haswell's northbridge ACPI), +coreboot's resource allocator identifies and uses two MMIO windows +below 4GB, but currently only one is declared in the ACPI _CRS. +Normally this isn't a problem, as coreboot is usually able to allocate +resources entirely in the (declared) lower MMIO window. But, this is +problematic when using top-down allocation, since coreboot assigns +resources to devices starting in the (undeclared) upper MMIO window, +which the OS does not consider a valid space. + +Linux will mostly handle this gracefully, and reassign BARs in the +lower MMIO address space. Windows does not, and will simply mark any +devices in the upper window as invalid or malfunctioning. + +To resolve this, add the dynamically-sized PM02 PCI MMIO window above +MMCONF to match the region used by coreboot's allocator. + +With this change, both MMIO windows are properly reported via _CRS, +allowing the OS to use coreboot's resource allocations properly. + +coreboot allocator: +[INFO ] * Base: 80000000, Size: 70000000, Tag: 200 [Window 1: 1.75GB] +[INFO ] * Base: f4000000, Size: a000000, Tag: 200 [Window 2: 160MB] + +kernel before: +[mem 0x80000000-0xefffffff window] [PM01: 1.75GB] +[mem 0xf4000000-0xfed44fff window] [TPM] + +kernel after: +[mem 0x80000000-0xefffffff window] [PM01: 1.75GB] +[mem 0xf4000000-0xfebfffff window] [PM02: 172MB] +[mem 0xfed40000-0xfed44fff window] [TPM] + +BUG=https://ticket.coreboot.org/issues/611 + +TEST=Build/boot google/lulu with top-down allocation enabled. +Verify kernel sees both MMIO windows and devices keep their coreboot- +assigned BARs. Verify Windows boots with functional i2c devices. + +Change-Id: I83fa8ca7f9edfd7d185895f8bbff15ee9895d1ff +Signed-off-by: Matt DeVillier +Reviewed-on: https://review.coreboot.org/c/coreboot/+/89588 +Tested-by: build bot (Jenkins) +Reviewed-by: Paul Menzel +Reviewed-by: Angel Pons +--- + .../intel/haswell/acpi/hostbridge.asl | 46 ++++++++++++++++++- + 1 file changed, 44 insertions(+), 2 deletions(-) + +diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl +index 3ecc5b3b36..509595b3b1 100644 +--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl ++++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl +@@ -14,6 +14,12 @@ Device (MCHC) + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { ++ Offset (0x60), // PCIEXBAR ++ PXEN, 1, // Enable ++ PXSZ, 2, // PCIEXBAR size ++ , 23, ++ PXBR, 10, // PCIEXBAR base ++ + Offset (0x70), // ME Base Address + MEBA, 64, + Offset (0xa0), // Top of Used Memory +@@ -125,12 +131,18 @@ Name (MCRS, ResourceTemplate() + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + +- // PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS) ++ // PCI Memory Region below MMCONF (TOLUD) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) +- ++#if CONFIG(SOC_INTEL_BROADWELL) ++ // PCI Memory Region above MMCONF (dynamic, based on ECAM size) ++ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, ++ Cacheable, ReadWrite, ++ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ 0x00000000,,, PM02) ++#endif + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, +@@ -164,6 +176,36 @@ Method (_CRS, 0, Serialized) + PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1 + PLEN = (PMAX - PMIN) + 1 + ++#if CONFIG(SOC_INTEL_BROADWELL) ++ // Set up PM02 region (MMCONF end to 0xFEBFFFFF) ++ CreateDwordField (MCRS, ^PM02._MIN, PM2B) ++ CreateDwordField (MCRS, ^PM02._MAX, PM2M) ++ CreateDwordField (MCRS, ^PM02._LEN, PM2L) ++ ++ // Calculate ECAM/MMCONF end address based on size bits in PCIEXBAR ++ // Bits [2:1] encode size: 00=256MB, 01=128MB, 10=64MB, 11=reserved ++ Local2 = ^MCHC.PXSZ ++ ++ // Populate based on ECAM size ++ If (Local2 == 0) { ++ // 256MB ECAM - no space for PM02 (would extend to 4GB boundary) ++ PM2L = 0 ++ } Else { ++ // 128MB or 64MB ECAM - there's space for PM02 ++ Local3 = CONFIG_ECAM_MMCONF_BASE_ADDRESS ++ If (Local2 == 1) { ++ // 128MB ECAM - ends at base + 0x08000000 ++ Local3 += 0x08000000 ++ } Else { ++ // 64MB ECAM (or reserved=3) - ends at base + 0x04000000 ++ Local3 += 0x04000000 ++ } ++ ++ PM2B = Local3 ++ PM2M = 0xFEBFFFFF // Just before chipset reserved (IOAPIC at 0xFEC00000) ++ PM2L = PM2M - PM2B + 1 ++ } ++#endif + Return (MCRS) + } + +-- +2.47.3 + diff --git a/patches/coreboot-25.09/0008-tree-Use-boolean-for-s3resume.patch b/patches/coreboot-25.09/0008-tree-Use-boolean-for-s3resume.patch new file mode 100644 index 000000000..0cb0b5185 --- /dev/null +++ b/patches/coreboot-25.09/0008-tree-Use-boolean-for-s3resume.patch @@ -0,0 +1,95 @@ +From b87a9795de20d2906c440174f28e4de172fe127e Mon Sep 17 00:00:00 2001 +From: Elyes Haouas +Date: Sat, 8 Feb 2025 12:19:28 +0100 +Subject: [PATCH 08/11] tree: Use boolean for s3resume + +Change-Id: I3e23134f879fcaf817cf62b641e9b59563eb643b +Signed-off-by: Elyes Haouas +Reviewed-on: https://review.coreboot.org/c/coreboot/+/86331 +Tested-by: build bot (Jenkins) +Reviewed-by: Angel Pons +Reviewed-by: Matt DeVillier +--- + src/northbridge/intel/haswell/broadwell_mrc/raminit.c | 4 ++-- + src/northbridge/intel/haswell/haswell_mrc/raminit.c | 2 +- + src/northbridge/intel/haswell/native_raminit/raminit_native.c | 2 +- + src/northbridge/intel/haswell/raminit.h | 2 +- + src/northbridge/intel/haswell/romstage.c | 2 +- + 5 files changed, 6 insertions(+), 6 deletions(-) + +diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +index e96f1a3adf..9114c26783 100644 +--- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c ++++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +@@ -310,7 +310,7 @@ static uint8_t map_to_pei_oc_pin(const uint8_t oc_pin) + return oc_pin >= USB_OC_PIN_SKIP ? PEI_USB_OC_PIN_SKIP : oc_pin; + } + +-static bool early_init_native(int s3resume) ++static bool early_init_native(bool s3resume) + { + printk(BIOS_DEBUG, "Starting native platform initialisation\n"); + +@@ -326,7 +326,7 @@ static bool early_init_native(int s3resume) + return cpu_replaced; + } + +-void perform_raminit(const int s3resume) ++void perform_raminit(const bool s3resume) + { + const struct northbridge_intel_haswell_config *cfg = config_of_soc(); + +diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c +index 62aa89ca79..edd9b049d4 100644 +--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c ++++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c +@@ -340,7 +340,7 @@ static uint8_t map_to_pei_oc_pin(const uint8_t oc_pin) + return oc_pin >= USB_OC_PIN_SKIP ? PEI_USB_OC_PIN_SKIP : oc_pin; + } + +-void perform_raminit(const int s3resume) ++void perform_raminit(const bool s3resume) + { + const struct device *gbe = pcidev_on_root(0x19, 0); + +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c +index 3ad8ce29e7..4ac220cb22 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c +@@ -163,7 +163,7 @@ static enum raminit_boot_mode do_actual_raminit( + return bootmode; + } + +-void perform_raminit(const int s3resume) ++void perform_raminit(const bool s3resume) + { + /* + * See, this function's name is a lie. There are more things to +diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h +index 6c76739e77..3f13a03db5 100644 +--- a/src/northbridge/intel/haswell/raminit.h ++++ b/src/northbridge/intel/haswell/raminit.h +@@ -17,6 +17,6 @@ struct spd_info { + void mb_get_spd_map(struct spd_info *spdi); + + void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg); +-void perform_raminit(const int s3resume); ++void perform_raminit(const bool s3resume); + + #endif /* NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H */ +diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c +index ce14915b2b..85fe967c7d 100644 +--- a/src/northbridge/intel/haswell/romstage.c ++++ b/src/northbridge/intel/haswell/romstage.c +@@ -27,7 +27,7 @@ void mainboard_romstage_entry(void) + haswell_early_initialization(); + printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); + +- const int s3resume = southbridge_detect_s3_resume(); ++ const bool s3resume = southbridge_detect_s3_resume(); + + elog_boot_notify(s3resume); + +-- +2.47.3 + diff --git a/patches/coreboot-25.09/0009-nb-intel-haswell-Factor-out-setup_sdram_meminfo.patch b/patches/coreboot-25.09/0009-nb-intel-haswell-Factor-out-setup_sdram_meminfo.patch new file mode 100644 index 000000000..520bbd7a4 --- /dev/null +++ b/patches/coreboot-25.09/0009-nb-intel-haswell-Factor-out-setup_sdram_meminfo.patch @@ -0,0 +1,432 @@ +From 3bbfbd37e14edeef66cc875080624554a5ed8448 Mon Sep 17 00:00:00 2001 +From: Angel Pons +Date: Wed, 15 Oct 2025 16:52:32 +0200 +Subject: [PATCH 09/11] nb/intel/haswell: Factor out `setup_sdram_meminfo()` + +Move the `setup_sdram_meminfo()` function to shared raminit code +to deduplicate it as well as to allow native raminit to make use +of it, which will be done in a follow-up. + +When consolidating the functions, the only functional difference +is that the Broadwell MRC.bin path reports memory frequencies in +MHz whereas the Haswell MRC.bin path reports them in MT/s. Since +this data is used to populate SMBIOS tables, which expect memory +frequencies in MT/s, using MT/s is the right choice. + +Given that SPD data is handled differently in the three RAM init +implementations (Haswell MRC, Broadwell MRC, native raminit), we +have to abstract the SPD data pointers a bit. This is done using +an array of pointers. + +While we're at it, add some TODO comments to note limitations of +the code. The idea is to fix those in follow-up commits. + +Change-Id: I1f81bf18a9e856d80f8e4d7bda65089e999957f6 +Signed-off-by: Angel Pons +Reviewed-on: https://review.coreboot.org/c/coreboot/+/89598 +Reviewed-by: Matt DeVillier +Reviewed-by: Nicholas Sudsgaard +Tested-by: build bot (Jenkins) +--- + .../intel/haswell/broadwell_mrc/raminit.c | 102 ++------------- + .../intel/haswell/haswell_mrc/raminit.c | 116 +++--------------- + src/northbridge/intel/haswell/raminit.h | 4 + + .../intel/haswell/raminit_shared.c | 97 +++++++++++++++ + 4 files changed, 131 insertions(+), 188 deletions(-) + +diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +index 9114c26783..98cfdcf412 100644 +--- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c ++++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +@@ -155,96 +155,6 @@ static void sdram_initialize(struct pei_data *pei_data) + report_memory_config(); + } + +-static uint8_t nb_get_ecc_type(const uint32_t capid0_a) +-{ +- return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; +-} +- +-static uint16_t nb_slots_per_channel(const uint32_t capid0_a) +-{ +- return !(capid0_a & CAPID_DDPCD) + 1; +-} +- +-static uint16_t nb_number_of_channels(const uint32_t capid0_a) +-{ +- return !(capid0_a & CAPID_PDCD) + 1; +-} +- +-static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) +-{ +- uint32_t ddrsz; +- +- /* Values from documentation, which assume two DIMMs per channel */ +- switch (CAPID_DDRSZ(capid0_a)) { +- case 1: +- ddrsz = 8192; +- break; +- case 2: +- ddrsz = 2048; +- break; +- case 3: +- ddrsz = 512; +- break; +- default: +- ddrsz = 16384; +- break; +- } +- +- /* Account for the maximum number of DIMMs per channel */ +- return (ddrsz / 2) * nb_slots_per_channel(capid0_a); +-} +- +-static void setup_sdram_meminfo(struct pei_data *pei_data) +-{ +- unsigned int dimm_cnt = 0; +- +- struct memory_info *mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); +- if (!mem_info) +- die("Failed to add memory info to CBMEM.\n"); +- +- memset(mem_info, 0, sizeof(struct memory_info)); +- +- const u32 ddr_frequency = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; +- +- for (unsigned int ch = 0; ch < NUM_CHANNELS; ch++) { +- const u32 ch_conf = mchbar_read32(MAD_DIMM(ch)); +- for (unsigned int slot = 0; slot < NUM_SLOTS; slot++) { +- const u32 dimm_size = ((ch_conf >> (slot * 8)) & 0xff) * 256; +- if (dimm_size) { +- struct dimm_info *dimm = &mem_info->dimm[dimm_cnt]; +- dimm->dimm_size = dimm_size; +- dimm->ddr_type = MEMORY_TYPE_DDR3; +- dimm->ddr_frequency = ddr_frequency; +- dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + slot)) & 1); +- dimm->channel_num = ch; +- dimm->dimm_num = slot; +- dimm->bank_locator = ch * 2; +- memcpy(dimm->serial, +- &pei_data->spd_data[ch][slot][SPD_DDR3_SERIAL_NUM], +- SPD_DDR3_SERIAL_LEN); +- memcpy(dimm->module_part_number, +- &pei_data->spd_data[ch][slot][SPD_DDR3_PART_NUM], +- SPD_DDR3_PART_LEN); +- dimm->mod_id = +- (pei_data->spd_data[ch][slot][SPD_DDR3_MOD_ID2] << 8) | +- (pei_data->spd_data[ch][slot][SPD_DDR3_MOD_ID1] & 0xff); +- dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; +- dimm->bus_width = MEMORY_BUS_WIDTH_64; +- dimm_cnt++; +- } +- } +- } +- mem_info->dimm_cnt = dimm_cnt; +- +- const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); +- +- const uint16_t channels = nb_number_of_channels(capid0_a); +- +- mem_info->ecc_type = nb_get_ecc_type(capid0_a); +- mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); +- mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a); +-} +- + #include + + /* Copy SPD data for on-board memory */ +@@ -433,5 +343,15 @@ void perform_raminit(const bool s3resume) + if (!s3resume) + save_mrc_data(&pei_data); + +- setup_sdram_meminfo(&pei_data); ++ const uint8_t *spd_data[NUM_CHANNELS][NUM_SLOTS] = { ++ [0] = { ++ [0] = pei_data.spd_data[0][0], ++ [1] = pei_data.spd_data[0][1], ++ }, ++ [1] = { ++ [0] = pei_data.spd_data[1][0], ++ [1] = pei_data.spd_data[1][1], ++ }, ++ }; ++ setup_sdram_meminfo(spd_data); + } +diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c +index edd9b049d4..7db6a1397f 100644 +--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c ++++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c +@@ -4,7 +4,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -183,101 +182,6 @@ static void sdram_initialize(struct pei_data *pei_data) + report_memory_config(); + } + +-static uint8_t nb_get_ecc_type(const uint32_t capid0_a) +-{ +- return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; +-} +- +-static uint16_t nb_slots_per_channel(const uint32_t capid0_a) +-{ +- return !(capid0_a & CAPID_DDPCD) + 1; +-} +- +-static uint16_t nb_number_of_channels(const uint32_t capid0_a) +-{ +- return !(capid0_a & CAPID_PDCD) + 1; +-} +- +-static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) +-{ +- uint32_t ddrsz; +- +- /* Values from documentation, which assume two DIMMs per channel */ +- switch (CAPID_DDRSZ(capid0_a)) { +- case 1: +- ddrsz = 8192; +- break; +- case 2: +- ddrsz = 2048; +- break; +- case 3: +- ddrsz = 512; +- break; +- default: +- ddrsz = 16384; +- break; +- } +- +- /* Account for the maximum number of DIMMs per channel */ +- return (ddrsz / 2) * nb_slots_per_channel(capid0_a); +-} +- +-static void setup_sdram_meminfo(struct pei_data *pei_data) +-{ +- struct memory_info *mem_info; +- struct dimm_info *dimm; +- int ch, d_num; +- int dimm_cnt = 0; +- +- mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); +- if (!mem_info) +- die("Failed to add memory info to CBMEM.\n"); +- +- memset(mem_info, 0, sizeof(struct memory_info)); +- +- const u32 ddr_freq_mhz = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; +- +- for (ch = 0; ch < NUM_CHANNELS; ch++) { +- const u32 ch_conf = mchbar_read32(MAD_DIMM(ch)); +- /* DIMMs A/B */ +- for (d_num = 0; d_num < NUM_SLOTS; d_num++) { +- const u32 dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256; +- if (dimm_size) { +- const int index = ch * NUM_SLOTS + d_num; +- dimm = &mem_info->dimm[dimm_cnt]; +- dimm->dimm_size = dimm_size; +- dimm->ddr_type = MEMORY_TYPE_DDR3; +- dimm->ddr_frequency = ddr_freq_mhz * 2; /* In MT/s */ +- dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + d_num)) & 1); +- dimm->channel_num = ch; +- dimm->dimm_num = d_num; +- dimm->bank_locator = ch * 2; +- memcpy(dimm->serial, +- &pei_data->spd_data[index][SPD_DDR3_SERIAL_NUM], +- SPD_DDR3_SERIAL_LEN); +- memcpy(dimm->module_part_number, +- &pei_data->spd_data[index][SPD_DDR3_PART_NUM], +- SPD_DDR3_PART_LEN); +- dimm->mod_id = +- (pei_data->spd_data[index][SPD_DDR3_MOD_ID2] << 8) | +- (pei_data->spd_data[index][SPD_DDR3_MOD_ID1] & 0xff); +- dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; +- dimm->bus_width = MEMORY_BUS_WIDTH_64; +- dimm_cnt++; +- } +- } +- } +- mem_info->dimm_cnt = dimm_cnt; +- +- const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); +- +- const uint16_t channels = nb_number_of_channels(capid0_a); +- +- mem_info->ecc_type = nb_get_ecc_type(capid0_a); +- mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a); +- mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a); +-} +- + /* Copy SPD data for on-board memory */ + static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi) + { +@@ -428,5 +332,23 @@ void perform_raminit(const bool s3resume) + if (!s3resume) + save_mrc_data(&pei_data); + +- setup_sdram_meminfo(&pei_data); ++ /* ++ * TODO: `setup_sdram_info()` uses SPD data to fill in various fields. However, ++ * even though Haswell MRC reads SPD data over SMBus, it does not pass the data ++ * back to coreboot. So, we currently only have SPD data for memory-down slots. ++ * ++ * We have to read the SPD data over SMBus again for coreboot to use it. But we ++ * can be smart and only read the bytes that `setup_sdram_meminfo()` needs. ++ */ ++ const uint8_t *spd_data[NUM_CHANNELS][NUM_SLOTS] = { ++ [0] = { ++ [0] = pei_data.spd_data[0], ++ [1] = pei_data.spd_data[1], ++ }, ++ [1] = { ++ [0] = pei_data.spd_data[2], ++ [1] = pei_data.spd_data[3], ++ }, ++ }; ++ setup_sdram_meminfo(spd_data); + } +diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h +index 3f13a03db5..2b80c24aba 100644 +--- a/src/northbridge/intel/haswell/raminit.h ++++ b/src/northbridge/intel/haswell/raminit.h +@@ -4,7 +4,9 @@ + #define NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H + + #include ++ + #include "chip.h" ++#include "haswell.h" + + #define SPD_MEMORY_DOWN 0xff + +@@ -17,6 +19,8 @@ struct spd_info { + void mb_get_spd_map(struct spd_info *spdi); + + void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg); ++void setup_sdram_meminfo(const uint8_t *spd_data[NUM_CHANNELS][NUM_SLOTS]); ++ + void perform_raminit(const bool s3resume); + + #endif /* NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H */ +diff --git a/src/northbridge/intel/haswell/raminit_shared.c b/src/northbridge/intel/haswell/raminit_shared.c +index 90fe1145cc..7a87359b63 100644 +--- a/src/northbridge/intel/haswell/raminit_shared.c ++++ b/src/northbridge/intel/haswell/raminit_shared.c +@@ -1,7 +1,13 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + ++#include ++#include ++#include + #include ++#include ++ + #include "chip.h" ++#include "haswell.h" + #include "raminit.h" + + void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg) +@@ -14,3 +20,94 @@ void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_ + memcpy(spdi->addresses, cfg->spd_addresses, ARRAY_SIZE(spdi->addresses)); + } + } ++ ++static uint8_t nb_get_ecc_type(const uint32_t capid0_a) ++{ ++ return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; ++} ++ ++static uint16_t nb_slots_per_channel(const uint32_t capid0_a) ++{ ++ return !(capid0_a & CAPID_DDPCD) + 1; ++} ++ ++static uint16_t nb_number_of_channels(const uint32_t capid0_a) ++{ ++ return !(capid0_a & CAPID_PDCD) + 1; ++} ++ ++static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a) ++{ ++ uint32_t ddrsz; ++ ++ /* Values from documentation, which assume two DIMMs per channel */ ++ switch (CAPID_DDRSZ(capid0_a)) { ++ case 1: ++ ddrsz = 8192; ++ break; ++ case 2: ++ ddrsz = 2048; ++ break; ++ case 3: ++ ddrsz = 512; ++ break; ++ default: ++ ddrsz = 16384; ++ break; ++ } ++ ++ /* Account for the maximum number of DIMMs per channel */ ++ return (ddrsz / 2) * nb_slots_per_channel(capid0_a); ++} ++ ++void setup_sdram_meminfo(const uint8_t *spd_data[NUM_CHANNELS][NUM_SLOTS]) ++{ ++ struct memory_info *mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); ++ if (!mem_info) ++ die("Failed to add memory info to CBMEM.\n"); ++ ++ memset(mem_info, 0, sizeof(struct memory_info)); ++ ++ /* TODO: This looks like an open-coded DIV_ROUND_CLOSEST() */ ++ const uint32_t ddr_freq_mhz = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; ++ ++ unsigned int dimm_cnt = 0; ++ for (unsigned int channel = 0; channel < NUM_CHANNELS; channel++) { ++ const uint32_t ch_conf = mchbar_read32(MAD_DIMM(channel)); ++ for (unsigned int slot = 0; slot < NUM_SLOTS; slot++) { ++ const uint32_t dimm_size = ((ch_conf >> (slot * 8)) & 0xff) * 256; ++ if (dimm_size) { ++ struct dimm_info *dimm = &mem_info->dimm[dimm_cnt]; ++ dimm->dimm_size = dimm_size; ++ /* TODO: Hardcoded, could also be LPDDR3 */ ++ dimm->ddr_type = MEMORY_TYPE_DDR3; ++ dimm->ddr_frequency = ddr_freq_mhz * 2; /* In MT/s */ ++ dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + slot)) & 1); ++ dimm->channel_num = channel; ++ dimm->dimm_num = slot; ++ dimm->bank_locator = channel * 2; ++ memcpy(dimm->serial, ++ &spd_data[channel][slot][SPD_DDR3_SERIAL_NUM], ++ SPD_DDR3_SERIAL_LEN); ++ memcpy(dimm->module_part_number, ++ &spd_data[channel][slot][SPD_DDR3_PART_NUM], ++ SPD_DDR3_PART_LEN); ++ dimm->mod_id = ++ (spd_data[channel][slot][SPD_DDR3_MOD_ID2] << 8) | ++ (spd_data[channel][slot][SPD_DDR3_MOD_ID1] & 0xff); ++ /* TODO: Should be taken from SPD instead */ ++ dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; ++ dimm->bus_width = MEMORY_BUS_WIDTH_64; ++ dimm_cnt++; ++ } ++ } ++ } ++ mem_info->dimm_cnt = dimm_cnt; ++ ++ const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); ++ const uint16_t num_channels = nb_number_of_channels(capid0_a); ++ ++ mem_info->ecc_type = nb_get_ecc_type(capid0_a); ++ mem_info->max_capacity_mib = num_channels * nb_max_chan_capacity_mib(capid0_a); ++ mem_info->number_of_devices = num_channels * nb_slots_per_channel(capid0_a); ++} +-- +2.47.3 + diff --git a/patches/coreboot-25.09/0010-nb-intel-haswell-Factor-out-report_memory_config.patch b/patches/coreboot-25.09/0010-nb-intel-haswell-Factor-out-report_memory_config.patch new file mode 100644 index 000000000..9c55576d7 --- /dev/null +++ b/patches/coreboot-25.09/0010-nb-intel-haswell-Factor-out-report_memory_config.patch @@ -0,0 +1,211 @@ +From 1730d05ec3ede0e878029cef82049d1d073db543 Mon Sep 17 00:00:00 2001 +From: Angel Pons +Date: Wed, 15 Oct 2025 17:10:30 +0200 +Subject: [PATCH 10/11] nb/intel/haswell: Factor out `report_memory_config()` + +Move the `report_memory_config()` function to shared raminit code, both +to deduplicate the code and to allow native raminit to make use of it. + +Change-Id: I8b3c695c0a266634a42b0303e4f1ea699301c26b +Signed-off-by: Angel Pons +Reviewed-on: https://review.coreboot.org/c/coreboot/+/89599 +Reviewed-by: Nicholas Sudsgaard +Reviewed-by: Alicja Michalska +Tested-by: build bot (Jenkins) +--- + .../intel/haswell/broadwell_mrc/raminit.c | 50 ------------------- + .../intel/haswell/haswell_mrc/raminit.c | 47 ----------------- + src/northbridge/intel/haswell/raminit.h | 1 + + .../intel/haswell/raminit_shared.c | 45 +++++++++++++++++ + 4 files changed, 46 insertions(+), 97 deletions(-) + +diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +index 98cfdcf412..8c0f5422df 100644 +--- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c ++++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +@@ -40,56 +40,6 @@ static void save_mrc_data(struct pei_data *pei_data) + pei_data->data_to_save_size); + } + +-static const char *const ecc_decoder[] = { +- "inactive", +- "active on IO", +- "disabled on IO", +- "active", +-}; +- +-/* +- * Dump in the log memory controller configuration as read from the memory +- * controller registers. +- */ +-static void report_memory_config(void) +-{ +- int i; +- +- const u32 addr_decoder_common = mchbar_read32(MAD_CHNL); +- +- printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", +- (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); +- +- printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", +- (addr_decoder_common >> 0) & 3, +- (addr_decoder_common >> 2) & 3, +- (addr_decoder_common >> 4) & 3); +- +- for (i = 0; i < NUM_CHANNELS; i++) { +- const u32 ch_conf = mchbar_read32(MAD_DIMM(i)); +- +- printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); +- printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); +- printk(BIOS_DEBUG, " enhanced interleave mode %s\n", +- ((ch_conf >> 22) & 1) ? "on" : "off"); +- +- printk(BIOS_DEBUG, " rank interleave %s\n", +- ((ch_conf >> 21) & 1) ? "on" : "off"); +- +- printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", +- ((ch_conf >> 0) & 0xff) * 256, +- ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", +- ((ch_conf >> 17) & 1) ? "dual" : "single", +- ((ch_conf >> 16) & 1) ? "" : ", selected"); +- +- printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", +- ((ch_conf >> 8) & 0xff) * 256, +- ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32", +- ((ch_conf >> 18) & 1) ? "dual" : "single", +- ((ch_conf >> 16) & 1) ? ", selected" : ""); +- } +-} +- + typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data); + + static void ABI_X86 send_to_console(unsigned char b) +diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c +index 7db6a1397f..d7439ca7b1 100644 +--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c ++++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c +@@ -58,53 +58,6 @@ static void prepare_mrc_cache(struct pei_data *pei_data) + pei_data->mrc_input, mrc_size); + } + +-static const char *const ecc_decoder[] = { +- "inactive", +- "active on IO", +- "disabled on IO", +- "active", +-}; +- +-/* Print out the memory controller configuration, as per the values in its registers. */ +-static void report_memory_config(void) +-{ +- int i; +- +- const u32 addr_decoder_common = mchbar_read32(MAD_CHNL); +- +- printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", +- DIV_ROUND_CLOSEST(mchbar_read32(MC_BIOS_DATA) * 13333 * 2, 100)); +- +- printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", +- (addr_decoder_common >> 0) & 3, +- (addr_decoder_common >> 2) & 3, +- (addr_decoder_common >> 4) & 3); +- +- for (i = 0; i < NUM_CHANNELS; i++) { +- const u32 ch_conf = mchbar_read32(MAD_DIMM(i)); +- +- printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); +- printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); +- printk(BIOS_DEBUG, " enhanced interleave mode %s\n", +- ((ch_conf >> 22) & 1) ? "on" : "off"); +- +- printk(BIOS_DEBUG, " rank interleave %s\n", +- ((ch_conf >> 21) & 1) ? "on" : "off"); +- +- printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", +- ((ch_conf >> 0) & 0xff) * 256, +- ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", +- ((ch_conf >> 17) & 1) ? "dual" : "single", +- ((ch_conf >> 16) & 1) ? "" : ", selected"); +- +- printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", +- ((ch_conf >> 8) & 0xff) * 256, +- ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32", +- ((ch_conf >> 18) & 1) ? "dual" : "single", +- ((ch_conf >> 16) & 1) ? ", selected" : ""); +- } +-} +- + /** + * Find PEI executable in coreboot filesystem and execute it. + * +diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h +index 2b80c24aba..e1b67e71d7 100644 +--- a/src/northbridge/intel/haswell/raminit.h ++++ b/src/northbridge/intel/haswell/raminit.h +@@ -19,6 +19,7 @@ struct spd_info { + void mb_get_spd_map(struct spd_info *spdi); + + void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg); ++void report_memory_config(void); + void setup_sdram_meminfo(const uint8_t *spd_data[NUM_CHANNELS][NUM_SLOTS]); + + void perform_raminit(const bool s3resume); +diff --git a/src/northbridge/intel/haswell/raminit_shared.c b/src/northbridge/intel/haswell/raminit_shared.c +index 7a87359b63..6fcb0ec98a 100644 +--- a/src/northbridge/intel/haswell/raminit_shared.c ++++ b/src/northbridge/intel/haswell/raminit_shared.c +@@ -21,6 +21,51 @@ void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_ + } + } + ++static const char *const ecc_decoder[] = { ++ "inactive", ++ "active on IO", ++ "disabled on IO", ++ "active", ++}; ++ ++/* Print out the memory controller configuration, as per the values in its registers. */ ++void report_memory_config(void) ++{ ++ const uint32_t addr_decoder_common = mchbar_read32(MAD_CHNL); ++ ++ printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", ++ DIV_ROUND_CLOSEST(mchbar_read32(MC_BIOS_DATA) * 13333 * 2, 100)); ++ ++ printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", ++ (addr_decoder_common >> 0) & 3, ++ (addr_decoder_common >> 2) & 3, ++ (addr_decoder_common >> 4) & 3); ++ ++ for (unsigned int i = 0; i < NUM_CHANNELS; i++) { ++ const uint32_t ch_conf = mchbar_read32(MAD_DIMM(i)); ++ ++ printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); ++ printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); ++ printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ++ ((ch_conf >> 22) & 1) ? "on" : "off"); ++ ++ printk(BIOS_DEBUG, " rank interleave %s\n", ++ ((ch_conf >> 21) & 1) ? "on" : "off"); ++ ++ printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", ++ ((ch_conf >> 0) & 0xff) * 256, ++ ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", ++ ((ch_conf >> 17) & 1) ? "dual" : "single", ++ ((ch_conf >> 16) & 1) ? "" : ", selected"); ++ ++ printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", ++ ((ch_conf >> 8) & 0xff) * 256, ++ ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32", ++ ((ch_conf >> 18) & 1) ? "dual" : "single", ++ ((ch_conf >> 16) & 1) ? ", selected" : ""); ++ } ++} ++ + static uint8_t nb_get_ecc_type(const uint32_t capid0_a) + { + return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT; +-- +2.47.3 + diff --git a/patches/coreboot-25.09/0011-Haswell-NRI-Print-and-fill-in-memory-related-info.patch b/patches/coreboot-25.09/0011-Haswell-NRI-Print-and-fill-in-memory-related-info.patch new file mode 100644 index 000000000..11ab7e981 --- /dev/null +++ b/patches/coreboot-25.09/0011-Haswell-NRI-Print-and-fill-in-memory-related-info.patch @@ -0,0 +1,88 @@ +From 70e79f43b17b0646ac71d0ff28bc8a6a932bd2d2 Mon Sep 17 00:00:00 2001 +From: Angel Pons +Date: Wed, 15 Oct 2025 17:47:50 +0200 +Subject: [PATCH 11/11] Haswell NRI: Print and fill in memory-related info + +Call the `report_memory_config()` and `setup_sdram_meminfo()` functions, +which were factored out into shared raminit code in previous patches. As +the SPD data is not readily available where `setup_sdram_meminfo()` gets +called, add a function to get it from the saved data, as it is available +in a global context. Technically speaking, the "mighty ctrl" variable is +also static (thus global), but it is only meant to be used within native +raminit code and is only static to avoid nuking the stack (it is huge). + +Change-Id: Ia2c0946f55748e38bb5ccb5cb06721aeb77527e7 +Signed-off-by: Angel Pons +Reviewed-on: https://review.coreboot.org/c/coreboot/+/89600 +Reviewed-by: Nicholas Sudsgaard +Tested-by: build bot (Jenkins) +--- + .../intel/haswell/native_raminit/raminit_native.c | 12 ++++++++++-- + .../intel/haswell/native_raminit/raminit_native.h | 1 + + .../intel/haswell/native_raminit/save_restore.c | 10 ++++++++++ + 3 files changed, 21 insertions(+), 2 deletions(-) + +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c +index 4ac220cb22..d5b5c117d6 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c +@@ -179,7 +179,7 @@ void perform_raminit(const bool s3resume) + const enum raminit_boot_mode bootmode = + do_actual_raminit(s3resume, cpu_replaced, orig_bootmode); + +- /** TODO: report_memory_config **/ ++ report_memory_config(); + + if (intel_early_me_uma_size() > 0) { + /* +@@ -208,5 +208,13 @@ void perform_raminit(const bool s3resume) + if (!s3resume) + save_mrc_data(); + +- /** TODO: setup_sdram_meminfo **/ ++ /* ++ * To avoid passing pointers around too much, get the SPD data ++ * from the saved data. It will always be present: a cold boot ++ * populates saved data from training results, and a fast boot ++ * or a S3 resume reads the saved data from the MRC cache. ++ */ ++ const uint8_t *spd_data[NUM_CHANNELS][NUM_SLOTS] = { 0 }; ++ reg_frame_get_spd_data(spd_data); ++ setup_sdram_meminfo(spd_data); + } +diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h +index b9e84a11df..53dbe4df28 100644 +--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h ++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h +@@ -504,6 +504,7 @@ void configure_refresh(struct sysinfo *ctrl); + struct register_save_frame *reg_frame_ptr(void); + size_t reg_frame_size(void); + uint32_t reg_frame_rev(void); ++void reg_frame_get_spd_data(const uint8_t *out_spd_data[NUM_CHANNELS][NUM_SLOTS]); + + uint32_t get_tCKE(uint32_t mem_clock_mhz, bool lpddr); + uint32_t get_tXPDLL(uint32_t mem_clock_mhz); +diff --git a/src/northbridge/intel/haswell/native_raminit/save_restore.c b/src/northbridge/intel/haswell/native_raminit/save_restore.c +index f1f50e3ff8..5be68808d8 100644 +--- a/src/northbridge/intel/haswell/native_raminit/save_restore.c ++++ b/src/northbridge/intel/haswell/native_raminit/save_restore.c +@@ -179,6 +179,16 @@ size_t reg_frame_size(void) + return sizeof(struct register_save_frame); + } + ++void reg_frame_get_spd_data(const uint8_t *out_spd_data[NUM_CHANNELS][NUM_SLOTS]) ++{ ++ const struct save_params *params = ®_frame_ptr()->params; ++ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) { ++ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) { ++ out_spd_data[channel][slot] = params->dimms[channel][slot].raw_spd; ++ } ++ } ++} ++ + typedef void (*reg_func_t)(const uint16_t offset, uint32_t *const value); + + static void save_value(const uint16_t offset, uint32_t *const value) +-- +2.47.3 + diff --git a/boards/UNMAINTAINED_kgpe-d16_server-whiptail/UNMAINTAINED_kgpe-d16_server-whiptail.config b/unmaintained_boards/UNMAINTAINED_kgpe-d16_server-whiptail/UNMAINTAINED_kgpe-d16_server-whiptail.config similarity index 100% rename from boards/UNMAINTAINED_kgpe-d16_server-whiptail/UNMAINTAINED_kgpe-d16_server-whiptail.config rename to unmaintained_boards/UNMAINTAINED_kgpe-d16_server-whiptail/UNMAINTAINED_kgpe-d16_server-whiptail.config diff --git a/boards/UNMAINTAINED_kgpe-d16_server/UNMAINTAINED_kgpe-d16_server.config b/unmaintained_boards/UNMAINTAINED_kgpe-d16_server/UNMAINTAINED_kgpe-d16_server.config similarity index 100% rename from boards/UNMAINTAINED_kgpe-d16_server/UNMAINTAINED_kgpe-d16_server.config rename to unmaintained_boards/UNMAINTAINED_kgpe-d16_server/UNMAINTAINED_kgpe-d16_server.config diff --git a/boards/UNMAINTAINED_kgpe-d16_workstation-usb_keyboard/UNMAINTAINED_kgpe-d16_workstation-usb_keyboard.config b/unmaintained_boards/UNMAINTAINED_kgpe-d16_workstation-usb_keyboard/UNMAINTAINED_kgpe-d16_workstation-usb_keyboard.config similarity index 100% rename from boards/UNMAINTAINED_kgpe-d16_workstation-usb_keyboard/UNMAINTAINED_kgpe-d16_workstation-usb_keyboard.config rename to unmaintained_boards/UNMAINTAINED_kgpe-d16_workstation-usb_keyboard/UNMAINTAINED_kgpe-d16_workstation-usb_keyboard.config diff --git a/boards/UNMAINTAINED_kgpe-d16_workstation/UNMAINTAINED_kgpe-d16_workstation.config b/unmaintained_boards/UNMAINTAINED_kgpe-d16_workstation/UNMAINTAINED_kgpe-d16_workstation.config similarity index 100% rename from boards/UNMAINTAINED_kgpe-d16_workstation/UNMAINTAINED_kgpe-d16_workstation.config rename to unmaintained_boards/UNMAINTAINED_kgpe-d16_workstation/UNMAINTAINED_kgpe-d16_workstation.config